A DMOS transistor is distinguished over a conventional MOS transistor (metal oxide semiconductor transistor) in that provided between the edge of the control gate and the drain region of the transistor is a drift zone, that is to say a zone in which the motion of the charge carriers is produced only by an electrical field applied between the oppositely disposed ends of the zone. In a lateral DMOS transistor (LDMOS transistor) the drift zone extends in the lateral direction, between the edge of the control gate and the drain region spaced therefrom in the lateral direction.
LDMOS transistors are used as high voltage components in which voltages, so-called drain voltages, of more than 100 volts, can be applied between the drain region and the source region of the LDMOS transistor. In addition LDMOS transistors are also used as high frequency power amplifiers with drain voltages in the range of between 10 volts and 20 volts as the operating voltage of the high frequency power amplifier.
Disposed in the drift zone of the LDMOS transistor is a weakly doped drain region which is near the surface, referred to for brevity as the LDD region (low doped drain region), which extends between the edge of the control gate and the drain region and which involves the same charge carriers as the drain region.
In the LDD region and the region below the control gate in which there is a highly doped region, referred to for brevity as the well, the flow of current is based in each case on different charge carriers. Thus in the LDD region the charge carriers are electrons while in the well they are holes or vice-versa. Therefore the LDD region and the well form a diode. Usually the well shares an external terminal with the source region so that the two are at the same potential. The LDD region is contacted by way of the drain region so that the drain voltage is applied at the end thereof that is towards the drain. If there is an open circuit in respect of the ‘diode’, that is to say a voltage is not present either at the control gate or at the LDD region (the voltage of the control gate, like the drain voltage, is measured with respect to the potential of the source region), then no voltage is dropped across the ‘diode’ consisting of the well and the LDD region, and a zone which is depleted in respect of charge carriers, the depletion zone, is formed at the junction from the well to the LDD region. A voltage drop occurs across the depletion zone and that has the result that the depletion zone remains limited to the region in the proximity of the junction. If now a drain voltage is applied the voltage drop across the depletion zone is increased. By virtue of the high drain voltages in LDMOS transistors high voltage drops occur in the depletion zone. Free charge carriers are produced in small amounts in the depletion zone by thermal excitation. If the voltage drops become too high the thermally excited free charge carriers are accelerated by the voltage drop in the depletion zone in such a way that, by virtue of colliding with atoms, they can break up the covalent bonds thereof. That produces new free charge carriers which in turn can break up covalent bonds and so forth. That results in what is known as an avalanche breakdown at the junction.
The described avalanche breakdown can have the result that high-energy charge carriers, so-called hot charge carriers, penetrate into the oxide layer between the well and the control gate (that oxide layer is referred to as the gate oxide). Those charge carriers are held fast in the gate oxide, which in time results in static charging of the gate oxide and thus impairs the properties of the LDMOS transistor. Likewise hot charge carriers penetrate into an oxide layer or nitride layer over the LDD region and are held fast there. This also results in static charging of the corresponding layer. Such charging in worst case scenarios can lead to a great reduction in or complete suppression of the flow of current through the DMOS transistor.
In addition the control gate and the gate-side edge of the LDD region, between which there is a part of the gate oxide layer, form a capacitor. With a high drain voltage a high voltage drop occurs across that capacitor, and that voltage drop can have the result that charge carriers accelerated by the voltage drop break through the oxide layer. That is then referred to as insulator breakdown.
One approach for overcoming the above-outlined disadvantages involves reducing the charge carrier concentration in the part of the LDD region in which there is a junction to the highly doped region beneath the control gate, to such an extent that that part is completely depleted of charge carriers if no voltage is applied at the control gate and a drain voltage is applied which is below the drain breakdown voltage (BVDS). The drain breakdown voltage is that voltage at which the depletion zone at the junction between the LDD region and the well extends to the source region. The reduced charge carrier density of the LDD region however results in an increase in the resistance of the LDD region in the on condition and thus a reduction in the current flowing through the drain region. The on condition of the LDMOS transistor is the condition in which formed beneath the control gate is a channel which is enriched with the charge carriers as are present in the source and in the drain regions, being referred to as the inversion layer. The inversion layer is formed when a voltage, referred to as the gate voltage, of a given value which is characteristic in respect of the transistor, occurs at the control gate. The drain current, that is to say the current flowing through the drain region, is reduced by the increased resistance on the on condition. In addition the slight density of free charge carriers by virtue of the reduced charge carrier concentration in the LDD region leads to increased sensitivity in relation to static charges of the oxide or nitride layer over the LDD region.
The state of the art is to be found in applications DE 100 04 387, DE 100 63 135 and WO 01/75979. In a situation involving the use of a high-resistance semiconductor substrate, the previously known LDMOS constructions, including the improved construction described in the above-identified invention, suffer from the disadvantage of a capacitance, which is very low even with low drain voltages (for example Vg=0-0.1V), between the undepleted LDD zone at the surface of the drift space and the substrate, in particular in the weakly doped region between the well region determining the threshold voltage of the control gate, and the highly doped drain region. So that, in spite of that low capacitance in accordance with the above-specified applications in the off condition (with the gate voltage Vg=0) and a drain voltage markedly below the drain breakdown voltage BVDS, total depletion of a part which is as large as possible of the drift space in respect of charge carriers and thus a low drain/gate capacitance and a drain breakdown voltage which is as high as possible with a field strength which is not excessively high at the thin gate insulator of the control gate are ensured, the number of free charge carriers in the LDD region and therewith also the conductivity in the ‘on’ condition must be suitably limited by a sufficiently low implantation dose in the LDD region. Besides the limited conductivity (high ‘on’ resistance Ron and poor current saturation performance), that low implantation dose also gives rise to an undesirably high level of sensitivity in respect of the LDMOS parameters (for example Ron, Ft and Fmax) in relation to static charges of the semiconductor surface, for example at a high drain voltage due to the injection of hot charge carriers from the LDD region into the electronic traps at the interface(s) of a passivation layer. In worst case scenarios such a charging effect can lead to a great reduction in or total pinch-off of the drain current at low drain voltages.